Document Type : Primary Research paper
Associate Professor, Department of Electronics and Communication Engineering, Erode Sengunthar Engineering College, Perundurai, Erode, Tamilnadu, India – 638057.
Associate Professor, Department of Electronics and Communication Engineering, R.V.R. & J.C. College of Engineering (Autonomous), Chowdavaram, Guntur-522019.
Assistant Professor, School of Electrical Engineering and Computing, Adama Science and Technology University, Adama, Ethiopia.
Assistant Professor, Department of EEE, St. Peter's Institute of Higher Education and Research,Tonakela Road, AVADI, Chennai - 54
Professor, Department of Electrical and Electronics Engineering, J.K.K. Munirajah College of Technology, T.N.Palayam, Erode, Tamilnadu, India - 638 506.
Associate Professor, Electrical and Electronic Engineering, Kumaraguru college of Technology, Coimbatore-641049.
In power electronics, current Internet of Things (IoT) progress is regarded as fundamental converters. IoT devices have a low response time, which may not be enough time to produce precise signals with stringent correspondence requirements. In reality, integrating IoT technology with existing grids remains a significant challenge. The operational and control approach of the matrix converter is established using an intelligent IoT device based on the innovation of the Robust Grid Unbalanced Control technology. Inverters work by providing a neutral point in the circuit with no current based on the design of the neutral clamping point, which is the primary portion of the loop. The direct current connection (DC) is not controlled in the current topology, but the proposed two-directional condenser system will. This procedure is doable. Robust Grid Unbalanced Control (RGUC) technology continuously loads Matrix Converter parameters to an IoT server. Simulation and hardware data support the suggested Efficient Grid Unbalanced Regulation framework, which has an average efficiency of 98.53 percent in the proposed control technology. The RGUC-based matrix converter is implemented using a low-cost, high-performance FPGA, and the experimental results are compared to those obtained through simulation.