Sensor Network Security In Low Power Hardware Development Through Ntpc

Document Type : Primary Research paper


1 PhD Research Fellow, Department of Computing, Mathematics and Physics , Høgskulen på Vestlandet, Inndalsveien 28, 5063 Bergen, Norway.

2 Assistant Professor, Department of Computer Science and Engineering, Jansons Institute of Technology, Karumathampatti, Tamil Nadu-641659.

3 Assistant Professor Senior, School of Computer Science and Engineering, Vellore Institute of Technology,Chennai Tamil Nadu 600127.

4 Dean,School of Technology & Engineering, ITM (SLS) Baroda University, Vadodara , Gujarat- 390510, lndia.

5 Assistant Professor, Department of Computer Science, St Francis de Sales College, Bangalore – 560100

6 Associate Professor, Department of Computer Science and Engineering , SRM Institute of Science and Technology, Modinagar, Ghaziabad, Uttar Pradesh-201204


Due to limited processor and Memory capability in a sensor, wireless sensor protection
necessitates cryptographic programs that are both simple & efficient. When building
decreased as well as resource-constrained devices, the Nth level trimmed polynomial circle
(NTPC) encryption technique was being found to provide further benefits even while
delivering equivalent levels of security to greater-complexity techniques. Despite earlier
studies that have focused on constructing NTPC software on a chip, this study
concentrated on NTRU method system design since hardware development seems to have a
considerably faster execution time over software configuration. In comparison to earlier
studies, the concentration herein seems to be on a review of several recommended practices
& proposed modifications, with such a particular emphasis on polynomials computing &
parameters determination. In hardware and software development, recommendations
regarding technique & parameter estimation are offered depends on the materials